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A Perspective on Router Architecture Challenges – Part 2: ASICs

by Greg.Hankins on ‎04-11-2012 01:08 PM (1,063 Views)

This the second part of my blog about some of the router architecture challenges that we’re facing from the perspective of a router vendor.  In the first part I talked about lookup and buffer memory architectures, and in this part we’ll go over some ASIC technology developments that we expect to use in the future.

The key ASIC challenge that we’re facing is integration.  The more functionality we can put on one chip, the more scalable we can make the system.  Today’s multiprotocol routers require complex packet parsing and deep packet header inspection – especially when you consider the variety of forwarding protocols that need to be supported in hardware (L2, IP, MPLS, etc) and the complex hashing functions used for load balancing all of these protocols evenly over members in a LAG.  Here are two examples that illustrate how integration affects how we design line cards.  The left picture is of our 8-Port 10 GbE oversubscribed L2/L3 switch line card.  Compare the complexity and number of components in the picture on the right of our 8-Port 10 GbE line-rate IP/MPLS router line card, and you’ll quickly get an idea of the integration challenges we have.  Board layout architecture must be carefully planned together with memory and ASIC components.


ASIC process geometry, which is the smallest dimension that can be drawn into the silicon to define a transistor, packaging and chip interconnects limit what we can do today.  Using more chips in parallel means higher cost, higher power consumption, higher heat dissipation and a lower overall MTBF.  For example, our 2-port 100 GbE card uses around 100 ICs (integrated circuits), we really need to reduce the number of components that we’re using!  Moore's Law states that the number of transistors on a chip will double approximately every two years, and so far this law has proven true.  Current generation ASICs use 45 nm and 32 nm technology, and the industry will use 22 nm technology as soon as it’s technically and commercially feasible.  The table below shows you what we’ve been able to do with some of the capacities in different technology generations that have increased the functionality that we can integrate into one ASIC.


When new process geometry is developed, component vendors focus on transistor density first.  The rest of the technologies (interconnection, on-chip memories, etc.) in the logic library are developed afterwards.  This means that the most current technology is used for general-purpose CPUs first.  Even though a new process geometry may be commercially available, we have to be able to integrate it.

The challenge with current ASIC technology is that it is optimized for either logic or memory requirements:

•    ASIC technology is logic driven (used in network processors)3d.png

•    Memory technology is memory driven (used in RAM)

New 3D multichip packaging technology is being developed that allows us to do both functions in the same physical package.  Instead of having one function in a chip, for example a network processor, we’ll be able to combine multiple different functions in the same chip.  Combining multiple ASICs or memories within the same package will make board layout simpler, will lower power consumption and heat dissipation, and most importantly will shorten the chip to chip interconnect to lower latency between components, especially memory.

I hope you enjoyed these two brief discussions on memory and ASIC technology.  I’m excited about the higher capacity and faster components that will allow us to continue to scale router density, lookup capacity and memory requirements to support multi-100 Gbps packet processing ASICs with custom lookup and buffering memory architectures.

For more information on Brocade’s high density 100 GbE solutions, please visit the Brocade MLX Series product page.

3D package image courtesy of IBM.