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Contributor
Posts: 23
Registered: ‎08-31-2014
Accepted Solution

BCM53101E Test mode configuration

Hi BRCM

we want to set BCM53101 GPHY port test mode1~mode4 for ethernet consistency test. from BCM53101E datasheet(53101E-DS06-RDS.pdf) page 197, we can get that

we must set Broadcom Test Register (Page 10h–14h: Address 3Eh–3Fh) bit7 to 1 to access shadow register. i.e. set it to 0x008b.

"Shadow Register Enable. Writing 1 to bit 7 of this register allows R/W access to the shadow registers located at addresses 1Eh–3Ch. "

so my question is how to set test mode1~mode4 for Page 10h–14h: Address 1Eh-3Ch? any detail description about this? we can't it from datasheet, need your feedback and thanks a lot.

Contributor
Posts: 23
Registered: ‎08-31-2014

Re: BCM53101E Test mode configuration

Hi ryanl​ and chris.huang

any update for this quesiton? thanks a lot.

Highlighted
Broadcom
Posts: 269
Registered: ‎02-15-2016

Re: BCM53101E Test mode configuration

Hi,

BCM53101 internal PHY is FE PHY, not GPHY.

The IEEE test configure is different between FE PHY and GPHY.

Please refer below registers setting for how to set FE PHY for IEEE conformance test.

Please be noted the below register offset is MII address.

SPI offset address=MII address *2, please double check 53101 datasheet Page10h-14h register map table.

1.1        UTP differential output voltage (Clause 9.1.2.2)

Register(MII address offset,not SPI offset)

Write value

Description

0x00

0x2100

Force 100BT, Full Duplex, which will generate

MLT -3 pattern to make measurements

1.2        Waveform overshoot (Clause 9.1.3)

Register

Write value

Description

0x00

0x2100

Force 100BT, Full Duplex, which will generate

MLT -3 pattern to make measurements

1.3        Return loss (Clause 9.1.5)

Register

Write value

Description

0x00

0x2100

Force 100BT, Full Duplex, which will generate

MLT -3 pattern to make measurements

0x18

0x4031

Force link

1.4        Rise/fall times (Clause 9.1.6)

Register

Write value

Description

0x00

0x2100

Force 100BT, Full Duplex, which will generate

MLT -3 pattern to make measurements

1.5        Duty cycle distortion  (Clause 9.1.8)

Register

Write value

Description

0x00

0x2100

Force 100BT, Full Duplex, which will generate

MLT -3 pattern to make measurements

0x18

0x1A36

Enable template pattern generate logic

0x1F

0x008B

Enable template register

0x15

0x4001

Generate 0101010101 pattern (Make measurements)

 
 

1.6        Jitter (Clause 9.1.9)

Register

Write value

Description

0x00

0x2100

Force 100BT, Full Duplex, which will generate

MLT -3 pattern to make measurements

1.7        Differential input impedance (Clause 9.2.2)

Register

Write value

Description

0x00

0x2100

Force 100BT, Full Duplex, which will generate

MLT -3 pattern to make measurements

1.8        Differential output voltage - Peak differential voltage (Clause 14.3.1.2.1)

Register

Write value

Description

0x00

0x0100

Force 10Base-T, FDX

0x18

0x1B31

Enable template pattern generate logic

0x1F

0x008B

Enable template register

0x15

0x0000

Generate 1010 pattern (Make measurements) or use traffic generator to send out 1010 pattern

0x15

0x4000

Generate 1111 pattern (Make measurements) or use traffic generator to send out 1010 pattern

1.9        Differential output voltage - Harmonics (Clause 14.3.1.2.1)

Register

Write value

Description

0x00

0x0100

Force 10Base-T, FDX

0x18

0x1B31

Enable template pattern generate logic

0x1F

0x008B

Enable template register

0x15

0x4000

Generate 1111 pattern (Conduct test)

1.10     Differential output voltage - Voltage template (Clause 14.3.1.2.1)

Register

Write value

Description

0x00

0x0100

Force 10Base-T, FDX

0x18

0x1B31

Enable template pattern generate logic

0x1F

0x008B

Enable template register

0x15

0x8000

Generate 1111 and 1010 pattern make measurements

 
 

  1.11     Differential Output Voltage - TP_IDL transition and voltage template(Clause 14.3.1.2.1)

Register

Write value

Description

0x00

0x0100

Force 10Base-T, FDX

0x18

0x4030

Force Link

Send “any (ping)” packet

Make EOP measurement

1.12     Differential Output Voltage – Test Link Pulse Voltage Template (Clause 14.3.1.2.1)

Register

Write value

Description

0x00

0x0100

Force 10Base-T, FDX

0x18

0x4030

Force Link and conduct test

1.13     Transmitter Differential Output Impedance -10BT (Clause 14.3.1.2.2)

Register

Write value

Description

0x00

0x0100

Force 10Base-T, FDX

0x18

0x4030

Force Link and conduct test

1.14     Output Timing Jitter 10BT (Clause 14.3.1.2.3)

Register

Write value

Description

0x00

0x0100

Force 10Base-T, FDX

0x18

0x1B31

Enable template pattern generate logic

0x1F

0x008B

Enable template register

0x15

0x8000

Generate 1111      and       1010      pattern      (Make measurements)

1.15     Transmitter Impedance Balance -10BT (Clause 14.3.1.2.4)

Register

Write value

Description

0x00

0x0100

Force 10Base-T, FDX

0x18

0x4030

Force Link and conduct test

1.16     Common Mode Output Voltage 10BT (Clause 14.3.1.2.5 )

Register

Write value

Description

0x00

0x0100

Force 10Base-T, FDX

 

0x18

0x1B31

Enable template pattern generate logic

0x1F

0x008B

Enable template register

0x15

0x0000

Generate 1010 pattern (Make measurements)

0x15

0x4000

Generate 1111 pattern (Make measurements)

1.17     Transmitter Common Mode Rejection 10BT (Clause 14.3.1.2.6)

Register

Write value

Description

0x00

0x0100

Force 10Base-T, FDX

0x18

0x1B31

Enable template pattern generate logic

0x1F

0x008B

Enable template register

0x15

0x0000

Generate 1010 pattern (Make measurements)

1.18     Receiver Differential Noise Immunity 10BT (Clause 14.3.1.3.2)

Register

Write value

Description

0x00

0x0100

Force 10Base-T, FDX

0x18

0x4030

Force Link and conduct test

1.19     Idle Input Behavior 10BT (Clause 14.3.1.3.3)

Register

Write value

Description

0x00

0x0100

Force 10Base-T, FDX

0x18

0x4030

Force Link and conduct test

1.20     Receiver Differential Input Impedance 10BT (Clause 14.3.1.4.4)

Register

Write value

Description

0x00

0x0100

Force 10Base-T, FDX

0x18

0x4030

Force Link and conduct test

1.21     Common Mode Rejection 10BT (Clause 14.3.1.4.5)

Register

Write value

Description

0x00

0x0100

Force 10Base-T, FDX

0x18

0x4030

Force Link and conduct test

Thanks,

Ryan

Contributor
Posts: 23
Registered: ‎08-31-2014

Re: BCM53101E Test mode configuration

Hi Ryan

Got it, and we will try to test it and thanks for your feedback.

发件人: ryanl

发送时间: 2016年5月16日 14:54

收件人: Joe Chan

主题: Re: - BCM53101E Test mode configuration

BCM53101E Test mode configuration

reply from ryanl <https://community.broadcom.com/people/ryanl?et=watches.email.thread> in Ethernet Switch Forums - View the full discussion <https://community.broadcom.com/message/25974?et=watches.email.thread#25974>

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